Neologic Ltd., a startup that makes the processors more efficient by reducing their transistor number, has collected 10 million US dollars in financial resources.
The company announced the round of Serie A today. It was described that Kompas VC led the investment with the participation of M Ventures, Maniv Mobility and Lool Ventures.
A processor consists of numerous transistor collections called gates. These goals are almost always made with a technology called CMOS. A CMOS gate contains two transistors with different electrical properties: One requires a positive load to switch from 0 to 1, while the other requires a positive load.
The Neologic based on Israel has developed a new chip design approach, which CMOS+referred to. According to the company, it combines standard CMOS gates with so-called gates with reduced complexity, which are produced with different technologies. According to Neologic, its approach can reduce the size of the processors by 40% and halve their electricity consumption.
One possibility, such as CMOS+ increases processing efficiency through CMOS+, is to reduce the number of transistors that must contain engineers in chips. According to Neologic, the technology can enable triple reduction in the transistor number of a chip under certain conditions. The fewer transistors are in a chip, the less electricity it consumes.
According to Neologic, its technology also improves the energy efficiency of the processors in another way.
By default, standard CMOS gates are limited, which means that you can only process a small number of data points in parallel. This slows down your processing speed. By increasing the fan, the engineers must implement complex circuit design that can significantly increase the power consumption of a chip.
Neologic says that its CMOS+ technology deals with these compromises with so -called one -stage gates. According to the company, these gates can process more data points in parallel than a standard cmos circuit while using less power.
The CMOS+ technology from Neologic also has a buffer design that is optimized for energy efficiency. Buffers are circuits in which a processor maintains the data that it actively uses in calculations. The company says that its design increases performance efficiency by increasing the surface of the buffer.
Neologic was founded in 2021 by Chief Executive Officer Avi Messica (in the picture, left) and the Chief Technology Officer Ziv Leshem (right). Messica told EE TIMES Europe that processors based on CMOS+ are suitable for the management of artificial intelligence models. The company believes that its technology can carry out less performance than graphics cards.
According to Neologic, its engineers use CMOS+to develop a number of central processing units for servers. The company hopes to produce a CPU with a core test CPU later this year. It is planned to provide CMOS+ processors in data centers by 2027.
Neologic will use its newly raised means to stop more engineers and accelerate its marketing efforts.
Photo: neological
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