Last week at IEEE International Solid State Circuits Conference, two of the greatest competitors in advanced chipmaking, Intel And TSMCdetailed the functions of the most important storage circuits, SramBuilt with their latest technologies, Intel 18a And TSMC N2. The ability of the chip makers to further reduce the scaling of circuits has slowed down over the years – but it was particularly difficult to reduce SRAM, which consists of large arrays of memory cells and support circuits.
The most densely packed SRAM block of the two companies delivers 38.1 megabits per square millimeterWith a memory cell with 0.021 square micrometers. This density corresponds to an increase of 23 percent for Intel and an improvement of 12 percent for TSMC. Something surprisingly the same morning Synops Unproved an SRAM design that achieved the same density with the previous generation of transistors, but operated with less than half of the speed.
The Intel and TSMC technologies are the first use of a new transistor architecture by the two companies called nanoblys. (Samsung switched to nano -leaves earlier.) In earlier generations, the electricity flows through the transistor via a fin -shaped sewer area. The design means that the increase in the current that a transistor can control – so that circuits can function faster or contain longer connections – to add more fins to the device. Nano -leaf devices eliminate the fins and exchange them for a stack of silicon tapes. It is important that the width of these nano leaves from device can be adjusted to the device so that the current can be increased more flexibly.
“Nano leaves seem to make it possible to scale better than in other generations,” says Jim Handy, Chief Analyst Memory Consulting company Objective Analyst.
Flexible transistors make smaller, better SRAM
An SRAM cell stores a little in a six-transistor circuit. But the transistors are not identical because they have different requirements for them. In a fin fet -based cell, this can mean that two pairs of the devices, each with two fins and the remaining two transistors, are built up with one fin each.
Nano-leaf devices offer “more flexibility for the size of the SRAM cell,” says Tsung-Yung Jonathan Chang, Senior Director at TSMC and IEEE-scholarshipiat. There are less unintentional differences between transistorsWith nano leaves, he says, a quality that improves the performance of SRAM's low voltage performance.
Engineers of both companies used the flexibility of the nano blade transistors. For the previously doubtful devices, which are referred to as pulldown and pass gate transistors, nano-leaf devices could be physically narrower than the two separate flowers they have replaced. But because the stack of nano leaves has more silicia overall, it can become more up -to -date. For Intel this meant up to a 23 percent reduction in the cell surface.
“Usually the BIT line has been on 256 bits for some time. For N2 … we can expand this to 512. It improves the density by almost 10 percent. ” -Sung-yung Jonathan Chang, TSMC
Intel detailed two versions of the storage group, a high density and a high -flow version, and the latter used the flexibility of the nano leaf even more advantage. In FinFet designs, the pass goal and the pull-down transistors have the same number of fins, but nano leaves enable Intel to make pulldown transistors wider than the pass gate devices, which leads to a lower minimal operating voltage.
In addition to Nanosheet transistors, Intel 18a is also the first technology that brings backside power delivery networks. Up to 18a, both the connections of the power supply connections, which are typically thick, and the finer signal compounds were built over silicon. Backside Power moves the power connections under the silicon, where they can be larger and less resistant and attract circuits through vertical compounds that appear through the silicon. The scheme also promotes the space for signal connections.
With FINFET devices, an SRAM transistor of a SRAM (PG) and Pud Down (PD) have to drive more electricity than other transistors, so that they are made with two fins. SRAM can have a more flexible design for nano blade transistors. In Intel's high-flow design, the PG device is wider than others, but the PD transistor is even wider than that to achieve more electricity. Intel
However, Backside Power is not a help to reduce the SRAM -Bit cell itself, said Xiaofei Wang, technology manager and manager at Intel, the engineers from IsSSCC. In fact, the use of backside power within the cell would expand its area by 10 percent, he said. Instead, the Intel team limited it to peripheral circuits and the scope of the Bit -Cell array. In the former, it helped to reduce the circuits because the engineers were able to build a key capacitor among the SRAM cells.
TSMC is not yet moving to backside power. But it was able to extract improvements at useful circuit level from nano blade transistors. Due to the transistor flexibility, the TSMC engineers were able to extend the length of the bit line, the connection through the cells. A longer Bit line links more SRAM cells and means that the memory needs fewer peripheral circuits, which shrinks the entire area.
“Usually the BIT line has been on 256 bit for some time,” says Chang. “For N2 … we can expand this to 512. It improves the density by almost 10 percent.”
Synopsys squeeze SRAM circuits
Synopsy that sells electronics design automation tools and circuit designs that engineers buy and integrate into their systems reached approximately the same density as TSMC and Intel, but today's most advanced finfet technology 3 nanometers. The company's density gain mainly came from the peripheral circuits that the SRAM array itself control, in particular from a so-called interface dual-rail architecture in combination with a gear lever.
In order to save electricity, especially for mobile processors, designers have started to advance the SRAM array and the peripheral circuits with different voltagesRahul Thukral, Senior Director of Product Management at Synopsy. They are referred to as a double splint and means that the periphery can work if necessary at a low voltage, while the SRAM corner cells run with a higher voltage, so that they are less likely to lose their bits.
However, this means that the tensions that the 1S and 0S represent in the SRAM cells do not match the tensions in the periphery. Designers therefore contain circuits that are referred to as the level Shifter to compensate for this.
The new Synopsys SRAM improves the density of memory by placing the Level Shifter circuits on the interface with the periphery instead of deep in the cellart and the circuits are smaller. What the company calls the “extended range” integrates more functions into the circuit, while Finfets are used with fewer fins, which leads to a more compact SRAM as a whole.
According to Thuirrral, however, the density is not the only point in her favor. “It enables the two rails to be far further apart,” he says, referring to the Bitzell tension and the peripheral voltage. The voltage on the bitzelles can run between 540 millivolt and 1.4 volts, while the voltage on the periphery can be up to 380 MV. This difference in voltage enables the SRAM to achieve good performance and at the same time minimize the power supply, he says. “If you put it down on really low tensions … it will bring the power supply to a lot that loves today's AI world,” he says.
When asked whether a similar circuit design could reduce SRAM in the future nano -leaf technologies, Thukral said: “The answer is 100 percent yes.”
Although Synopsy has managed to meet TSMC and Intel to the density, the offer became much slower. The maximum of the Synopsy SRAM was 2.3 gigahertz compared to 4.2 GHz for the fastest version of TSMCS SRAM and 5.6 GHz for Intel.
“It is impressive synopsy can reach the same density with 3 Nm, and it is a frequency that will be relevant for the mass market silicon for this node in the long term,” says Ian Cutress, Chief Analyst at more than bogs. “It also shows how much process nodes are rarely static and new, dense designs for things like SRAM still appear.”
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