By using the advanced functions of the Palladium Z3 Enterprise emulation platform and the use of the DPA app of the new Dynamic Power Analysis (dpa), Cadence and NVIDIA can now provide hardware-accelerated dynamic performance analysis of AI designs with billions of allows and for the first time span billion of cycles with up to 97 % accuracy.
This is a significant milestone and enables semiconductor and systems developers who aim at KI-, machine learning (ML) and GPU-intended applications in order to design more energy-efficient systems and accelerate their time for the market.
The complexity and the arithmetic requirements of the advanced semiconductors and systems provide designers who have not yet been able to not precisely predict their electricity consumption under realistic conditions.
Conventional electricity analysis tools cannot go beyond a few hundred thousand cycles without requiring impractical schedules, but in close cooperation with Nvidia, Cadence was able to enable these challenges through hardware-supported electricity acceleration and parallel processing innovations.
“Cadence and Nvidia build on our long history to introduce transformative technologies that were developed through deep cooperation,” said Dhiraj Goswami, Corporate Vice President and General Manager at Cadence. “This project has redefined borders and processed billions of cycles in just two to three hours. This enables customers to safely achieve aggressive performance and electricity targets and to accelerate their time until silicon.”
“While the era of the AI infrastructure of agents and the next generation is developing quickly, the engineers need demanding tools to design more energy-efficient solutions,” said Narendra Konda, Vice President of Hardware Engineering at NVIDIA. “By combining Nvidia's accelerated computer skills with the EDA leadership of Cadence, we promote the hardware acceleration performance in order to enable more precise efficiency in accelerated computer platforms.”
The Palladium Z3 platform uses the DPA app to appreciate the electricity consumption under real workloads, so that functions, electricity consumption and performance can be checked before the opening if the design can still be optimized.
It will be particularly useful in AI, ML and GPU control applications, in which early power modeling increases energy efficiency and at the same time avoids delays from over or underpinned semiconductors.
Palladium dpa is integrated into the Cademedace analysis and implementation solution so that designers can carry out the most efficient possible design of silicon and system constructions during the entire design process.